In many gigahertz-class high-speed data transmissions, a transmitter converts parallel data into serial data and transmit the converted serial data to a receiver by a serial transmission. The receiver receives the transmitted serial data and converts it into parallel data.
In a usual receiver used in such high-speed serial data transmissions, serial data are sampled using a clock signal recovered from serial data. Further, data of the serial data are received and recovered in synchronization with a clock signal on the receiver side. A clock recovery circuit recovers a clock signal from a received serial data. A data recovery circuit recovers data of the received serial data using the recovered clock signal.
The clock recovery circuit needs to generate a stable synchronized clock signal by eliminating a jitter component included in the received data, to sample the serial data by using the recovered clock signal. Therefore, the clock recovery circuit is required to have a filter circuit for jitter elimination.
The filter circuit parallelizes information on a transition edge of the received serial data, and performs a digital filtering processing on the parallelized data. The digital filtering processing generates a stable synchronized clock signal not having jitter components in the range from a low frequency to a high frequency.
A signal used for a high-speed serial data transmission includes high-level EMI noise. Accordingly, a technique for reducing the EMI noise has been developed. In the technique, the transmitter side uses a spread spectrum clock (hereinafter referred to as a “SSC”) for a serial-data generation clock.
In the SSC, the frequency of transmission data transmitted using a spread spectrum clock signal is obtained by frequency-modulating at a frequency of several kilohertz, for example, with respect to a clock of the receiver side, which ranges from several hundreds ppm to several thousands ppm. Therefore, the transmission data can be regarded data modulated at very high frequency. Accordingly, the clock recovery circuit requires a function of tracking jitter components modulated at high frequency.
Thus, the clock recovery circuit adopting the SSC technique needs to perform conflicting operations. One of the operations is elimination of the jitter components in the range from a low frequency to a high frequency. The other of the operations is tracking of a signal modulated at a high frequency.
Japanese Patent Application Publication No. 2007-60652 (hereinafter, referred to as “JP2007-60652”) discloses a clock data recovery circuit adopting the SSC technique. In the clock data recovery (hereinafter, referred to as “CDR”) circuit, a sampler samples serial data in response to a recovery clock signal, and generates a serial sampling pulse. A CDR loop converts the serial sampling pulse into parallel data. The CDR loop generates multiple relatively-slow phase signals by using the parallel data. Further, the CDR loop generates a relatively-fast phase control signal by using the multiple relatively-slow phase signals. In addition, a phase interpolator advances or delays the phase of a reference clock signal, which is provided from outside, in response to the phase control signal. As a result, a recovery clock signal is generated.
The CDR circuit can operate at a high speed with minor phase errors.
However, in the CDR circuit disclosed in the patent document, the phase control signal generated by the CDR loop operates at a frequency corresponding to only ½n of the frequency of the reference clock signal, where “n” is a positive integer. Even when four-phase clock signals having 90° phase differences are used, the phase control signal operates at a frequency corresponding to only 2/n of the frequency of the reference clock signal.
When a bit rate of high-speed serial data is 1 GHz and the high-speed serial data are converted into parallel data of 10 bits (n=10), for example, the CDR circuit operates only at a frequency of 50 MHz (200 MHz at most).
As a result, in the CDR circuit, the amount of adjustment, which can be performed at one time, increases. It causes increase in clock jitters, with increase of the transmission rate of high-speed serial data transmission, or with increase of the number of bits of serial/parallel conversion.